Method for forming a void free via

ABSTRACT

A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug.  
     The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

FIELD OF THE INVENTION

[0001] The present invention relates to the manufacture of semiconductordevices, and more particularly to a method for forming vias insemiconductor devices.

BACKGROUND OF THE INVENTION

[0002] A continuing trend in semiconductor integrated circuitmanufacturing is to make more powerful and complex integrated circuitdevices in a smaller area. Manufacturers achieve this objective bymaking individual circuit component sizes smaller and by locating thesecomponents closer together. Millions of active and passive circuitcomponents, such as transistors, capacitors, and resistors are formed ona semiconductor substrate. These circuit components are formedelectrically isolated from each other on the substrate and later areinterconnected to form functional circuits. The quality of theseinterconnecting structures greatly affects the performance, andreliability of the completed integrated circuits.

[0003] Often the interconnections are fabricated as a multilayerstructure having alternating layers of patterned metallic and dielectricmaterials. The dielectric layers, frequently a form of silicon oxide,serve to separate the conductors, both vertically and horizontally, andvery small, vertical metal filled vias in the dielectric layers providea means of interconnection between the metal levels.

[0004] In multilevel structures, the metal conductors may include a baseor seed layer, a bulk conductor layer, a capping layer, and a barrierlayer, and the sum of these layers is referred to as a metal stack. Themetal stack is formed on a dielectric layer and then etched, through theuse of photolithographic techniques, to define the interconnectingstructure.

[0005] A typical via structure formed on a horizontal metalinterconnection layer stack includes a via hole through one or moredielectric layers, and a conductive metallic plug system in the viahole.

[0006] At present, Aluminum and aluminum alloys are widely used as thebulk conductors, and tungsten is widely used as the metal plug for thevia in the art of integrated circuit manufacturing.

[0007] Structural defects in the system of the interconnecting metallayer stack and the metallic plug in the vias can cause performance andreliability problems in the projected life span of the semiconductorintegrated circuit device. One structural defect manifests itself in theform of voids at the interface region between the metallic plug and themetal stack. Application Ser. No. 10/091,789 identifies one root causeof void formation in a tungsten/aluminum system and the solution to thecause. In that invention, a process is described to arrest the metalintrusion from the metal stack into the vias. Application Ser. No.10/091,789 is hereby incorporated by reference in its entirety.

[0008] In this invention, Applicants identify another cause of voidformation at the interface of the tungsten plugs and the aluminum metalstack and describes a solution to eliminate or to reduce its harmfuleffect.

SUMMARY OF THE INVENTION

[0009] It is an object of the current invention to provide a method forelimination or reduction of void formation at the bottom of via holes inmultilevel integrated circuit devices.

[0010] It is an object of the invention to identify the root cause ofvoid formation at the bottom of via holes, and to provide a method foreliminating or reduce the source of the failure.

[0011] It is an object of the invention to provide an improvedmanufacturing process for via formation.

[0012] It is an objective of the invention to provide a manufacturingprocess which does not slow throughput.

[0013] It is an object of the invention to provide a method formanufacture of semiconductor devices that improves yield andreliability.

[0014] It is an object of the invention to provide a method forelimination or reduction of void formation at the bottom of via holesthat is applicable to different metal stacks.

[0015] It is an object of the invention to provide an interconnectionmetallization, including titanium aluminide, wherein good integrity ofthe via against void formation at the bottom of the via holes isexhibited.

[0016] The above and other objectives of the invention will be met bydisclosing a process whereby void formation at the bottom of the viasare eliminated or reduced. The thickness of Ti seed layer is controlled,thereby discouraging the reaction between the Ti seed layer and theAluminum bulk layer to form titanium aluminide compound of which thevolume is less than the ingredient titanium and aluminum atoms.

[0017] By eliminating or reducing the cause of excessive titaniumaluminide, the number and the size of voids at the bottom of the viaholes may be eliminated or reduced, and in turn yield and reliability ofthe device is significantly enhanced. The method is applicable todifferent metal stacks.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a cross sectional view of an interconnecting metal stackas deposited.

[0019]FIG. 2 is a cross section of an interconnecting metal stack postanneal and titanium aluminide formation.

[0020]FIG. 3 is a cross section of via formation on the interconnectingmetal stack.

[0021]FIG. 4 is a cross section of a via after via metal deposition.

DETAILED DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 depicts a stack of metal layers in one embodiment of thisinvention. The metal stack layer is to form a horizontal interconnectingline in a multilayered structure. The aluminum layer 106 is the bulkconductor layer, deposited on the surface of a dielectric layer 101formed on a semiconductor substrate (not shown). The aluminum layer issandwiched by a titanium layer 102 on the bottom and a titanium layer104 on the top.

[0023] Overlying the top titanium layer is a titanium nitride layer 108.The primarily function that the titanium nitride layer 108 serves inthis structure is an antireflection coating that aids in defining andforming the interconnecting metal line.

[0024] Following the photolithography process and the etching processthat form the stacked metal line of titanium nitride 108, titanium 104,aluminum 106, and titanium 103, the semiconductor substrate undergoes anannealing process at an elevated temperature. The resulting structure isdepicted in FIG. 2.

[0025]FIG. 2 depicts the result of the annealing process, where thetitanium layers and the aluminum layer react to form titanium aluminide(TiAl₃) layers 103 and 105. The titanium aluminide layers areadvantageous as an etch stop, an electro-migration barrier, and abarrier against aluminum extrusion into vias that are formed later inthe manufacturing process.

[0026]FIG. 2 also depicts a dielectric layer 109 on top of the titaniumnitride layer 108. Vias through which the metal stack 100 iselectrically connected to the upper conductive layers (not shown) areformed in the dielectric layer 109 as shown in FIG. 3.

[0027]FIG. 3 depicts two via holes at the completion of the via etchprocess. The dimensions in the drawing do not necessarily correspond toany actual via holes and are only for the purpose of illustration.Depending on the design rules, the aspect ratio of via holes, i.e. theratio of the depth of the via hole 1 to the diameter of the via hole d,may vary. At present, an integrated circuit device with 0.18 μm designrules may include via holes with aspect ratio ranging from 1.4 to 2.4.

[0028] Under a typical manufacturing condition, the via etch process maygenerate via holes that resemble one or both of the vias in FIG. 3. Viahole 310 in the drawing depicts one type of via holes of which theintegrity of the grain structure of the titanium aluminide layer at thebottom of the via hole is preserved and the titanium aluminide layercompletely shields the underlying aluminum.

[0029] Via hole 320 in the drawing depicts the second type of via holesof which grains of the titanium aluminide layer 105 are missing and thealuminum layer 106 is uncovered at the area of the missing grains. Atthe bottom of the via holes, the titanium nitride layer 108 is usuallyremoved by the etching process.

[0030]FIG. 4 depicts the portion of the integrated circuit deviceincluding via 320 at the completion of via metal deposition. The viametal includes a thin titanium layer 201, a thin titanium nitride layer203 and a tungsten plug 205.

[0031] The titanium nitride layer in this structure serves as adiffusion barrier. The function of the titanium will be described inmore detail in the following sections.

[0032] Titanium is a chemically active metallic element and serves atleast two purposes in this structure.

[0033] First, titanium readily bonds with the walls of the via holes andwith the surface of the titanium nitride layer 203 and as a result goodadhesion between the walls of the via hole and the titanium nitridelayer 203 may be achieved.

[0034] Secondly, titanium reacts with and reduces metal oxide such asaluminum oxide (Al₂O₃) that forms at the surface of the metal stack 100at the bottom of the via holes. In order to form good ohmic contactbetween the metal stack 100 and the metal in the via, it is criticalthat the top surface of the metal stack 100 be free of metal oxide filmthat is non-conducting. It is desirable, therefore, to have sufficientamount of titanium at the bottom of the via hole for the getteringaction to take place.

[0035] One phenomenon often overlooked by the manufacturers ofintegrated circuit devices is that this seed titanium layer will readilyreact with the aluminum layer of the metal stack 100 through anyopenings in the titanium aluminide layer 105 as depicted in FIG. 3.

[0036] It is well known in the art of metallurgy that the size of thetitanium aluminide molecule is less than the volume sum of itsconstituent titanium and aluminum atoms. When the reaction that formstitanium aluminide takes place in a closed area such as at the interfaceof the metal stack 100 and the bottom of the via 320, a void that isproportional to the volume of formed titanium aluminide will also form.

[0037]FIG. 4 depicts such a reaction that forms voids initiated at thearea 200 where some grains from the titanium aluminide layer 105 aremissing. If the condition is favorable for the reaction to continue, thevoid will grow in size and excessive growth of the voids will cause thesemiconductor integrated circuit device to fail.

[0038] If the failure is detected at the integrated circuitmanufacturer's factory before it is incorporated into an electronicsystem, it is counted as a yield loss. More seriously, the void may besmall at the initial test stage and escape detection and subsequently,during actual operation in the field, continues to grow and eventuallycauses of the entire system to fail.

[0039] It is discovered by the Applicants that one can detect theexistence of voids caused by this mechanism with a simple process ofbaking the semiconductor substrate and monitoring the value of the viaresistance. Baking the semiconductor integrated circuit device at 200°C. for 72 hours is sufficient to reveal the existence and the growth ofvoids. If the via resistance increases substantially following thebaking step, it is evident that the reaction is continuing and apotential via failure exists. As an example, the Applicants discoveredthat an increase of 0.19 ohms in via resistance following the 72 hourbake almost always indicates a visually (via electron microscopy)detectable void at the bottom of the via.

[0040] Two approaches can prevent the failure caused by excessive voidgrowth. The first is to maintain the integrity of the titanium aluminidelayer 105 so the titanium layer 201 does not come in direct contact withthe underlying aluminum. This approach is not always practical becausein order to ensure the completely removed of dielectric material 109from the via hole, a certain over etch is necessary in at the via etchprocess and this over-etch often damages the titanium aluminide layer105, resulting in missing grains at the bottom of the via holes.

[0041] A preferable approach to eliminate the over growth of the void isto reduce the amount of the titanium available for the reaction bylimiting the thickness of the titanium layer 201.

[0042] It is discovered by the Applicants that when the titanium layer201 is not thicker than about 100 Å, no serious void formation will takeplace such that the reliability of the semiconductor integrated circuitmay be compromised. When the titanium layer 201 is thinner than about 55Å, the void formation problem can be practically arrested.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising a. a semiconductor substrate having a top surface and abottom surface, b. a first dielectric layer formed on the top surface ofthe semiconductor substrate, c. a metal stack formed on the surface ofthe first dielectric layer, the metal stack including i. a firstintermetallic compound layer, ii. an metallic layer overlying the firstintermetallic compound layer, iii. a second intermetallic compound layeroverlying the metallic layer, and iv. a diffusion barrier layeroverlying the second intermetallic compound layer, d. a seconddielectric layer overlying the metal stack and a portion of the firstdielectric layer, the second dielectric layer having a top surface, e. avia region in the second dielectric layer having a wall region and abottom region, the bottom region being in contact with the secondintermetallic compound layer, the via region being free of dielectricmaterial, and f. a layer of seed layer overlying at least a portion ofthe wall region and the bottom region, the thickness of the seed layerbeing between 40 and 100 angstroms.
 2. A semiconductor integratedcircuit device according to claim 1, wherein the semiconductor substrateincludes silicon material.
 3. A semiconductor integrated circuit deviceaccording to claim 1, wherein the first layer and the second dielectriclayer include silicon dioxide.
 4. A semiconductor integrated circuitdevice according to claim 1, wherein the first intermetallic compoundlayer and the second intermetallic compound layer include titaniumaluminide.
 5. A semiconductor integrated circuit device according toclaim 1, wherein the seed layer includes titanium.
 6. A semiconductorintegrated circuit device according to claim 1, wherein the seed layeris between 40 and 55 angstroms.
 7. A semiconductor integrated circuitdevice according to claim 1, wherein the metallic layer includesaluminum.
 8. A semiconductor integrated circuit device, comprising a. asilicon substrate having a top surface and a bottom surface, b. a firstsilicon dioxide layer formed on the top surface of the siliconsubstrate, c. a metal stack formed on the surface of the first silicondioxide layer, the metal stack including i. a first titanium aluminidelayer, ii. an aluminum layer overlying the first titanium aluminidelayer, iii. a second titanium aluminide layer overlying the aluminumlayer, and iv. a first titanium nitride layer overlying the secondtitanium aluminide layer, d. a second silicon dioxide layer overlyingthe metal stack and a portion of the first silicon dioxide layer, thesecond silicon dioxide having a top surface, e. a via region in thesecond silicon dioxide layer having a wall region and a bottom region,the bottom region being in contact with the second titanium aluminidelayer, the via region being free of silicon dioxide, and f. a layer oftitanium overlying at least a portion of the wall region and the bottomregion, the thickness of the titanium layer being between 40 and 100angstroms.
 9. A process for fabricating a semiconductor integratedcircuit device, comprising a. providing a semiconductor substrate havinga top surface and a bottom surface, b. forming a first dielectric layeron the top surface of the semiconductor substrate, c. forming a metalstack on the surface of the first dielectric layer, the metal stackincluding i. a first intermetallic compound layer, ii. an metallic layeroverlying the first intermetallic compound layer, iii. a secondintermetallic compound layer overlying the metallic layer, and iv. afirst diffusion barrier layer overlying the second intermetalliccompound layer, d. forming a second dielectric layer overlying the metalstack and a portion of the first dielectric layer, the second dielectriclayer having a top surface, e. forming a via region in the seconddielectric layer having a wall region and a bottom region, the bottomregion being in contact with the second intermetallic compound layer,the via region being free of dielectric material, and f. forming a seedlayer overlying at least a portion of the wall region and the bottomregion, the thickness of the seed layer being between 40 and 100angstroms.
 10. A process for fabricating semiconductor integratedcircuit device according to claim 9, wherein the semiconductor substrateincludes silicon material.
 11. A process for fabricating semiconductorintegrated circuit device according to claim 9, wherein the first layerand the second dielectric layer include silicon dioxide.
 12. A processfor fabricating semiconductor integrated circuit device according toclaim 9, wherein the first intermetallic compound layer and the secondintermetallic compound layer include titanium aluminide.
 13. A processfor fabricating semiconductor integrated circuit device according toclaim 9, wherein the seed layer includes titanium.
 14. A process forfabricating semiconductor integrated circuit device according to claim9, wherein the seed layer is between 40 and 55 angstroms.
 15. A processfor fabricating semiconductor integrated circuit device according toclaim 9, wherein the metallic layer includes aluminum.
 16. A process fordetecting a void in a semiconductor integrated circuit device having avia structure, comprising: a. providing a semiconductor integratedcircuit device having a via structure, b. measuring the electricalresistance of the via structure, recording the first measured viaresistance, c. baking the semiconductor integrated circuit device at anelevated temperature, d. measuring the electrical resistance of the viastructure, recording the second measured via resistance, e. subtractingthe first measured via resistance from the second measured viaresistance, recording the balance, and f. continuing processing thesemiconductor integrated circuit device when the balance is smaller thana pre-selected value.
 17. A process for detecting a void in asemiconductor integrated circuit device having a via structure of claim16, wherein the pre-selected value is about 0.19 ohms per via.